This invention relates to programmable logic array integrated circuits, and more particularly to programmable logic array integrated circuits with improved arrangements of the programmable logic elements and improved interconnections between those elements.
Programmable logic arrays are known in which substantial numbers of relatively elementary individual programmable logic elements are provided in a two-dimensional array. The array also includes a grid of intersecting signal conductors for conducting logic signals to, from, and between the programmable logic elements.
As integrated circuit fabrication techniques progress, it becomes possible to put more and more programmable logic elements on a chip. As the number of elements increases, it becomes important to improve the techniques used to interconnect them. For example, it is important to provide enough interconnection pathways between the programmable logic elements so that the capabilities of those elements can be fully utilized and so that complex logic functions (requiring concatenation of programmable logic elements) can be performed, without providing so many such pathways that there is a wasteful excess of this type of resource. Similarly, as the number of programmable elements increases, the complexity of the logic which can be performed also increases. But this in turn tends to increase the complexity of the task of programming the circuit unless additional logical structure is included in the circuit to help correspondingly structure the programming task.
There is always room for further improvement, however, and there are some situations in which the provision of additional or alternative types of interconnections between the logic modules would have benefits sufficient to justify the additional circuit and programming complexity. Such additional interconnection paths may be desirable for making frequently needed kinds of interconnections, for speeding certain kinds of interconnections, for allowing short distance connections to be made without tying up more general purpose and therefore long distance interconnection resources, etc. There is also a continuing demand for logic devices with larger capacity. This produces a need to implement logic functions more efficiently and to make better use of the portion of the device which is devoted to interconnecting individual logic modules.
Another challenge that must be met in PLD design is the connection of internal logic elements to the input/output pins of the chip, as discussed, for example, in commonly assigned, co-pending patent application Ser. No. 08/497,504, filed Jun. 30, 1995, and incorporated by reference herein. For example, larger PLDs are generally provided with a large number of external input/output pins for transmitting signals off-chip, but the interconnect structure of such PLDs is such that a particular logic element on the chip has direct access to a very limited number of I/O pins. A typical large PLD may have as many as two-hundred to four-hundred or more I/O pins. Such devices are also provided with an intricate global interconnect structure for allowing individual functional elements on the PLD to communicate signals with all other elements on the PLD. For reasons of conserving chip area, this global interconnect structure is connected to the external pins in a limited way such that a particular logic element on the chip has direct access to a very limited number of I/O pins. If a signal from a logic element must be transmitted to an I/O pin to which that logic element does not have direct access, the signal must be routed through an additional logic element that has direct access to that I/O pin. This can create problems in PLD reprogrammability and modifiability of certain logic designs. For example, if a minor modification in an application requires that a logic signal be routed to a different I/O pin, ideally the PLD should be easily reprogrammable to accommodate this modification. However, with the limitations of some prior art PLDs, rerouting a logic signal to a different I/O pin could require use of additional logic elements. If these logic elements were unavailable because they were being used in other parts of the design, modification of the chip to reroute the output signal might be impossible.
From the above it is seen that an improved programmable logic device is desired.